The present invention generally relates to electronic design automation (EDA) tools, and, more particularly to an EDA tool for designing an integrated circuit.
Integrated circuits (ICs) including system-on-chips (SoCs) include many small to medium sized embedded memories such as static random access memories (SRAMs), dynamic random access memories (DRAMs), read-only memories (ROMs), and flash memories for storing information. For example, in current state-of-the-art SoCs, forty to eighty percent of the circuit area is dedicated to embedded memories. Such memories are high density physical structures.
With memories, there is a high probability of complex defects such as coupling faults and pattern-sensitive faults in addition to simple stuck-at faults. Thus, embedded memories are an important factor in SoC yield and therefore it is important to have a testing and repairing mechanism for the embedded memories that can detect and repair faulty rows and columns by replacing the faulty rows and columns with redundant rows and columns. Redundant rows and columns are spare rows and columns used to replace rows and columns having faulty memory cells or faulty addresses.
One way to test SoC memories it to use an automatic test equipment (ATE). The ATE generates test patterns, i.e., test vectors, based on testing algorithms such as March and checkerboard algorithms. The ATE provides the test patterns, and evaluates response vectors generated by the embedded memories based on the test patterns. However, technological advancements have dramatically improved the performance, such as operational frequency, functionality, and density of embedded memories, making it difficult for ATE to perform at-speed testing.
One conventional technique for at-speed testing and repairing of embedded memories is to use one or more built-in self-test (BIST) controllers, i.e., BIST logic units, where one BIST logic unit can test multiple embedded memories.
The embedded memories often different dimensions such as number of words (i.e., word count), number of memory blocks, column multiplexing factor, number of rows, and number of columns (indicative of data width). Embedded memories that have similar dimensions are grouped together to reduce the hardware required for testing the embedded memories. Such grouping of embedded memories is also referred to as memory ganging. The embedded memories having the same memory dimensions can have a common scrambling unit, a common chip select unit, a common comparator, and a common repairing unit. However, memories of different dimensions, require dedicated scrambling units, repairing units, and comparators.
FIG. 1 illustrates a schematic block diagram of a conventional SoC 100 having a BIST logic unit 102 for testing and repairing embedded memories of the SOC 100. The BIST logic unit 102 is added in to the design of the SoC 100 by an EDA tool during the design stage of the SoC 100. The EDA tool groups the embedded memories of the SoC 100 based on the memory dimensions of the embedded memories. The SoC 100 shown has first through third memories 104-108.
Table A illustrates the memory dimensions, viz. the count of words, data width, column multiplexing factor, and count of memory blocks of the first through third memories 104-108.
TABLE AColumnCount ofCount ofDatamultiplexingmemoryMemorywordswidthfactorblocksFirst memory847421Second memory848021Third memory848021
In this example, the second and third memories 106 and 108 have the same dimensions. The first memory 104 has a data width of 74 bits, which is different from the width of the second and third memories 106 and 108. With this design, the second and third memories 106 and 108 are grouped together by the EDA tool during the design stage as a first set of memories 110. Each of the first through third memories 104-108 includes redundant rows and columns. The EDA tool replaces faulty memory cells or faulty addresses of the first through third memories 104-108 with the redundant rows and columns of the respective memories based on the number of redundant rows and columns of the first through third memories 104-108.
In FIG. 1, the BIST logic unit 102 includes a BIST testing unit 112, a first testing logic unit 114 for dedicated testing and repairing of the first memory 104, and a second testing logic unit 116 for testing and repairing of the first set of memories 110 (i.e., the second and third memories 106, 108). The first testing logic unit 114 includes a first scrambling unit 118, a first comparator 120, and a first repairing unit 122, while the second testing logic unit 116 includes a common scrambling unit 124, a common chip select unit 126, a common comparator 128, and a common repairing unit 130.
The BIST logic unit 102 further includes a control logic unit (not shown) for generating control signals for initiating and terminating the BIST and controlling the use of the testing algorithms for generation of test vectors.
The testing unit 112 includes a data generator (not shown) such as an automatic test pattern generator (ATPG) for generating first and second sets of test vectors based on the testing algorithms. The testing unit 112 is connected to the first memory 104 by way of the first testing logic unit 114 for providing the first set of test vectors to the first memory 104, and connected to the first set of memories 110 by way of the second testing logic unit 116 for providing the second set of test vectors to the first set of memories 110.
The first scrambling unit 118 is connected to the first memory 104 for generating a first set of addresses of the first memory 104 that are indicative of memory cells of the first memory 104 that undergo BIST for fault detection.
The first comparator 120 is connected to the first memory 104 for receiving a first set of response vectors generated by the first memory 104 based on the first set of test vectors. The first comparator 120 compares the first set of response vectors with the first set of test vectors received from the testing unit 112 and generates a first set of comparison signals that is indicative of pass or fail statuses of the memory cells of the first memory 104.
The first repairing unit 122 is connected to the first memory 104 for replacing faulty addresses or faulty memory cells of the first memory 104 with redundant rows and columns of the first memory 104 based on the first set of comparison signals and a redundancy analysis algorithm, such as essential spare pivoting, row first, and column first algorithms.
The common scrambling unit 124 is connected to the first set of memories 110 for generating a second set of addresses for the first set of memories 110 for BIST. The second set of addresses includes addresses indicative of memory cells of the first set of memories 110, and hence, the second and third memories 106 and 108, that undergo BIST for fault detection. The common chip select unit 126 selects the second and third memories 106 and 108 for BIST.
The common comparator 128 is connected to the first set of memories 110 for receiving a second set of response vectors generated by the first set of memories 110 based on the second set of test vectors. The common comparator 128 compares the second set of response vectors with the second set of test vectors received from the testing unit 112 and generates a second set of comparison signals indicative of pass or fail statuses of the memory cells of the first set of memories 110.
The common repairing unit 130 is connected to the first set of memories 110 for replacing faulty addresses or faulty memory cells of the second and third memories 106 and 108 with redundant columns and rows of the second and third memories 106 and 108, respectively, based on the second set of comparison signals and the redundancy analysis algorithm.
The BIST logic unit 102 initiates a BIST operation when it receives a power-on reset (POR) signal. The testing unit 112 generates and provides the first set of test vectors to the first memory 104 based on the first set of addresses and the second set of test vectors to the first set of memories 110 based on the second set of addresses. The first memory 104 and the first set of memories 110 are tested in parallel. The common chip select unit 126 enables sequential testing of the embedded memories of the first set of memories 110. The first comparator 120 compares the first set of response vectors with the first set of test vectors and generates the first set of comparison signals. The common comparator 128 compares the second set of response vectors with the second set of test vectors and generates the second set of comparison signals. After testing, the first repairing unit 122 repairs the first memory 104 and the common repairing unit 130 repairs the first set of memories 110.
The conventional technique groups the embedded memories of the SoC 100 only when the embedded memories have the same dimensions. Thus, the BIST logic unit 102 includes different testing logic units for testing and repairing the embedded memories with different dimensions, which increases the hardware and area of the SoC 100.
Generally, it is desirable that the testing time of the largest embedded memory exceeds the testing time of the remaining embedded memories of the SoC 100. However, the conventional technique does not group the embedded memories such that their testing time is less than the testing time of the largest embedded memory. Further, adding additional or different types of embedded memories to the SoC 100 or resizing existing embedded memories usually results in inserting more testing logic units into the design.
Therefore, it would be advantageous to have a system and method that groups embedded memories of an integrated circuit that have the same memory dimensions, reduces hardware and area required for test logic without affecting overall testing time, and provides good scalability.